Dr. Sheikh Wasmir Hussain Assistant Professor
Ph.D. (NIT Meghalaya) Department of Electronics & Communication Engineering- NA
- wasmir@iiitg.ac.in
Joined the Institute in August 2023
About
Hello, and welcome to my homepage. I’m an Assistant Professor in the Department of Electronics and Communication Engineering (ECE) at IIIT Guwahati.
- Joined IIIT Guwahati, Guwahati, India in August 2023
- Served as a Senior Research Scientist in the MeLoDe (Memory Logic Devices & Logic Design) Laboratory, Dept. of Electrical Engineering, IIT Bombay, from October 2021 to August 2023
- Completed Ph.D. (VLSI Design), Thesis on High Performance Content Addressable Memory, in March 2022, from Dept. of Electronics and Communication Engineering (ECE), NIT Meghalaya
- Obtained M.Tech (ECE - VLSI Design) from NIT Meghalaya
- Earned B.E. (ECE) from NIE Mysore, under Visvesvaraya Technological University (VTU), Belagavi, India
- Dropped out after 1st year from B.Sc. (Hons.) in Mathematics, at University of Delhi (DU), New Delhi, India
Research Interests
Area of Research
- Semiconductor Memories
- CMOS Digital Circuit Techniques
- Low Power VLSI Design
- Secure ASIC Circuits
Research Profile Link
Institute Responsibility
- Associate Sports Co-ordinator, IIIT Guwahati, April 2024 to November 2025
- Member of Faculty Advisory Board, IIIT Guwahati, April 2024 to November 2025
- M.Tech (ECE) Admission Co-ordinator, VLSI & Embedded System, IIIT Guwahati, June to August 2024
- Member of Committee to Propose New Courses/Specializations for M.Tech (ECE) Program M.Tech , IIIT Guwahati, September 2025 to Till Date
Tapeout Work
- Associated with MeLoDe Lab, IIT Bombay: One time programmable (OTP) memory, physical unclonable function (PUF) and secure circuits in SCL 180-nm technology [Role: Circuit Verification & Layout Design]
- Associated with Research Lab, NIT Meghalaya: Pre-charge free dynamic content addressable memory in SCL 180-nm technology [Role: Circuit Verification & Layout Design]
Invited Talk
- Invited Talk on "Content Addressable Memory: A Design Perspective From Exact to Approximate Searching Architecture", Workshop on Emerging Cutting Edge Technologies in CMOS: Trends and Challenges, Dec. 11 – 15, 2024, NIT Silchar, Silchar.
- Expert Speaker on "Cadence Tutorial", Accelerate Vigyan SERB Workshop on Custom IC Design using EDA, Feb. 27 – Mar. 5, 2022, IIIT Pune, Pune.
- Invited Talk on "Low-Power and High-Speed Nanometer-CMOS CAMs", Faculty Development Program (FDP), Apr. 26 – May 8, 2021, GITA Autonomous College, Bhubaneshwar.
Teaching
At IIIT Guwahati, I teach the following Undergraduate & Postgraduate Courses:
- Theory
- Basic Electronic Circuits (Winter 2023-24, 2024-25)
- Digital Design (Monsoon 2024-25, 2025-26)
- Analog Circuits (Monsoon 2024-25, 2025-26)
- Tutorial
- Electrical Circuit Analysis Tutorial (Monsoon 2022-23)
- Laboratory
- Analog Integrated Circuit (Monsoon 2022-23)
- Digital Design (Monsoon 2023-24, 2024-25, 2025-26)
- Embedded Systems Laboratory (Winter 2023-24, 2024-25)
- Seminar
- M. Tech ECE & CSE Seminar (Monsoon 2022-23)
[Course Details Can be Found in GitHUB Link]
Supervision (Thesis, Dissertation & Others)
Doctoral (Ph.D.)
- Mr. Arnav Banerjee
- Ongoing Since February 2024
- Research Area: Low-Power and/or High-Speed Associative Memory for Data Processing and In-Memory Computing Applications
Post-Graduate (M.Tech)
- Mr. Saphaba Yambem (2024-26 Batch)
- Thesis Ongoing: Towards Precharge – Free Content Addressable Memory (CAM)
- Mr. Mamun Mansur (2024-26 Batch)
- Thesis Ongoing: Data Compression using Associative Memory (AM)
- Ms. Priyanshi Malviya (2023-25 Batch)
- Thesis Completed: A Low Power SRAM Based CAM For Networking Applications
- Currently a Ph.D. Scholar at Dept. of Electrical Engineering, IIT Gandhinagar
- Mr. Jayabrata Chakraborty (2023-25 Batch)
- Thesis Completed: High-Speed Associative Memory Based on Selective-charging Match-Line Scheme
- Currently a Layout Engineer at Youzentech Technologies, Bangaluru
Undergraduate (B.Tech)
- Mr. Bheemuni Harshavardhan Reddy (2022-26 Batch)
- Dissertation Ongoing: Ternary Logic Based Combinational Circuit Designs
- Dissertation Completed: Memristor-Based Performance-Efficient Combinational Circuit Designs
- Mr. Shivendu Chourasia (2022-26 Batch)
- Dissertation Ongoing: From 6T Static Random Access Memory (SRAM Cell) to Memory Array: Stability, PVT, and Read/Write Performance Analysis
- Mr. Podili Manikanta (2022-26 Batch)
- Dissertation Ongoing: Low-Power Contention-Free Single-Phase Split-Controlled Flip-Flop (SCFF) Design
- Mr. Banoth Siddartha (2022-26 Batch)
- Dissertation Ongoing: Design and Analysis of Conventional and Multi-Transistor SRAM Cells with Emphasis on Noise Margins and Read Disturbance
- Mr. Aayush Mishra (2021-25 Batch)
- Dissertation Completed: An Exact Search Accelerator Based on Content Addressable Memory (CAM)
- Currently an MBA Student at IIFT Kolkata
- Mr. Arnav Das (2021-25 Batch)
- Dissertation Completed: Content-Addressable Memory Using Single Search-Line/Bit-Line Core Cell
- Mr. Sangam Chauhan (2021-25 Batch)
- Dissertation Completed: High-Speed Associative Memory Based on Selective-Charging Match Line Scheme
Internship
- Mr. Jayabrata Chakraborty
- Topic: 8*4 Conventional CAM design
- Affiliation: M.Tech (VLSI), IIIT Guwahati
- Period: 11 May - 29 July, 2024
- Ms. Promita Das
- Topic: CMOS Design Using Cadence
- Affiliation: B.Tech (ECE), Assam Don Bosco University
- Period: 8 July - 10 August, 2024
Achievement, Award & Fellowship
- Resource Person, Representation of R&D Works, G20 Research and Innovation Initiative Gathering (RIIG) Summit & Research Ministers’ Meeting, Jul. 2023, IIT Bombay, Mumbai.
- Resource Person, Representation of R&D Works, India Semiconductor Mission’s Semicon India Conference, July 2023, Mahatma Mandir, Gandhinagar.
- First Prize in Oral Presentation in Engineering Discipline, 2nd Research Conclave, Feb. 28–Mar. 1, 2021, NIT Meghalaya, Shillong.
- Among Top 12 Ph.D. Thesis Works in Student Research Form, 34th International Conference on VLSI Design & 20th International Conference on Embedded Systems 2021 (VLSID 2021), Feb. 20–24, 2021, India (Virtual).
- International Travel Support, from MeitY, Govt. of India for Presenting Research Paper at IEEE 6th International Conference on Engineering Technologies and Applied Sciences (ICETAS), Dec. 20–21, 2019, UTMKL, Kuala Lumpur.
- JRF and SRF, under NIT Meghalaya from MoE (then MHRD), Govt. of India, Fellowships during Ph.D., Jul. 2017–Jul. 2021.
- GATE Fellowship, under NIT Meghalaya from MoE (then MHRD), Govt. of India, Teaching Assistant during M.Tech, Jul. 2015 – May 2017.
- GATE-2015 Qualified, 6592 All India Rank (AIR) in ECE Discipline, 96.18 Percentile.
- Merit Cum Means (MCM) Scholarship, under Minority & OBC, Govt. of Manipur for Pursuing B.E., 2010 – 2013.
- AIEEE-2009 Qualified, 31579 AIR and 47 Manipur State Rank in OBC Category.
- Most Regular Student Award, 100% Attendance Record during Academic Session 2006–2007 at Herbert School, Imphal.
- Academic Prizes, Appreciations, and Awards from various state organizations, Manipur, India for merit in High School Board and Higher Secondary School Council Examinations, 2006–2008.
Publication
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Journal
- S. W. Hussain, T. V. Mahendra, S. Mishra, and A. Dandapat, "Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine", Integration the VLSI Journal,98, (2024), pages. 102213, Elsevier
- S. W. Hussain, T. V. Mahendra, S. Mishra, and A. Dandapat, "SMS-CAM: Shared matchline scheme for content addressable memory", Integration the VLSI Journal,88, (2023), pages. 70-79, Elsevier
- S. W. Hussain, T. V. Mahendra, S. Mishra, and A. Dandapat, "Match-line control unit for power and delay reduction in hybrid CAM", IET Circuits, Devices & Systems,15 (3), (2021), pages. 272-283, Wiley
- S. W. Hussain, T. V. Mahendra, S. Mishra, and A. Dandapat, "Low-power content addressable memory design using two-layer PN match-line control and sensing", Integration the VLSI Journal,75, (2020), pages. 73-84, Elsevier
- T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, "A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM)", Journal of Information Science and Engineering,36(5), (2020), pages. 1035-1053, Institute of Information Science, Academia Sinica
- S. Mishra, T. V. Mahendra, S. W. Hussain, and A. Dandapat , "The analogy of matchline sensing techniques for content addressable memory (CAM)", IET Computers & Digital Techniques,14(3), (2020), pages. 87-96, Wiley
- T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, "Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications", IEEE Transactions on Circuits and Systems I: Regular Papers,67(7), (2020), pages. 2345-2357, IEEE
- T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, "Low discharge precharge free matchline structure for energy-efficient search using CAM", Integration the VLSI Journal,69, (2019), pages. 31--39, Elsevier
- S. W. Hussain, T. V. Mahendra, S. Mishra, and A. Dandapat, "Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory", IEEE Transactions on Consumer Electronics,64 (3), (2018), pages. 301--309, IEEE
- T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, "Precharge free dynamic content addressable memory", IET Electronics Letters,54 (9), (2018), pages. 556--558, Wiley
Conference
- A. Banerjee and S. W. Hussain,, "An 8T Single Bit-Line Content Addressable Memory Cell for High-Performance Searching Applications", 36th International Conference on Microelectronics (ICM), 2024, Qatar,NA, (2024), pages. 1-6, IEEE
- S. W. Hussain, T. V. Mahendra, S. Mishra, and A. Dandapat, "Pseudo-Static Master-Slave Match-Line Scheme for Sustainable-Performance and Energy-Efficient Content Addressable Memory", IEEE Region 10 Symposium (TENSYMP),Dhaka, (2020), pages. 258-261, IEEE
- S. W. Hussain, T. V. Mahendra, S. Mishra, and A. Dandapat, "Efficient Matchline Controller for Hybrid Content Addressable Memory", IEEE 2nd International Conference on Electronics and Communication Engineering (ICECE),Xi'an, (2019), pages. 418--422, IEEE
- T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, "Low Match-Line Voltage Swing Technique for Content Addressable Memory", 7th International Conference on Smart Computing & Communications (ICSCC),Sarawak, (2019), pages. 1--5, IEEE
- S. W. Hussain, T. V. Mahendra, S. Mishra, and A. Dandapat, "A Quasi-Static Storage and Decision Block for Performance-Efficient Content Addressable Memory", 6th International Conference on Engineering Technologies and Applied Sciences (ICETAS),Kuala Lumpur, (2019), pages. 1-6, IEEE
- T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, "A Low-Power Split-Controlled Single Ended Storage Content Addressable Memory", IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS),Rourkela, (2019), pages. 369-372, IEEE
- T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, "Design and Implementation of Drivers and Selectors for Content Addressable Memory (CAM)", IEEE 2nd International Conference on Electronics and Communication Engineering (ICECE),Xi'an, (2019), pages. 216-220, IEEE
- T. V. Mahendra, S. W. Hussain, S. Mishra, and A. Dandapat, "Performance Analysis of N-CAM, P-CAM and TG-CAM Using 45-nm Technology", International Conference on Intelligent Computing and Control Systems (ICCS),Madurai, (2019), pages. 621--625, IEEE
- K. B. Singh, S. W. Hussain, T. V. Mahendra and C. V. Rama Rao, "Implementation of OFDM and Pulsed-OFDM", 15th International Conference on Information Technology (ICIT),Bhubaneswar, (2016), pages. 110--113, IEEE
Others
- S. W. Hussain, "Match Line Controlled Content Addressable Memory Low Power and High Speed Searching", Shodhganga : a reservoir of Indian theses @ INFLIBNET,Shillong, (2022), pages. NA, National Institute of Technology (NIT) Meghalaya