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Department of Computer Science and Engineering

Indian Institute of Information Technology Guwahati

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Dr. Arijit Nath
Dr. Arijit Nath Assistant Professor
PhD (IIT Guwahati)

Department of Computer Science and Engineering
About

I am an Assistant Professor in the Department of CSE at Indian Institute of Information Technology, Guwahati. I joined IIITG in July, 2023. I did B.Tech from National Institute of Technology, Silchar; M.Tech from Tezpur University and PhD from Indian Institute of Technology, Guwahati in 2013, 2016 and 2023, respectively. My area of research is computer architecture with a special interest in the emerging memory technologies. Apart from professional activities, I like to play sports like tennis, table tennis and badminton. I am also a sincere learner of yoga and meditation.

I am actively looking for motivated and hardworking PhD students (full-time and part-time) to work in the broad area of computer systems and architecture. Interested students can apply before 12 Jan, 2026 using the link.

Research Interests

  1. Computer Architecture
  2. Emerging Memory Technologies
  3. Memory System Design
  4. Intermittent Computing

Teaching

At IIITG, I have taught the following courses:

  1. IT Workshop I (Java Programming)
  2. Computer Organization and Architecture

Supervision

PhD Supervision

  • Mr. Chetan Kumar (Ongoing)

B.Tech Supervision

  • Harsh Raj
  • Jitendra Meena
  • Ankur Srivastava
  • Nandini Modi


M.Tech Supervision

  • Abarnan Rajkhowa
  • Puja Panja



Invited Talk

  • Invited as a resource person to deliver a talk on "Latest Trends in CSE and its future prospects", at University of Science and Technology (USTM), Meghalaya. 
  • Invited as a resource person to deliver a talk on "Emerging Memory Technologies: Shaping the Next Era of Data Processing", at Girijananda Choudhury University, Assam
  • Invited as a distinguished speaker for the webinar on “Future-Ready Computing: The Memory Shift”, organized by  Microsoft Student Chapter at VIT-AP University,

Achievements

  •  Manuscript titled "HiParEnc : An effective History based Partial Re-encryption strategy to improve lifetime of Non-Volatile Main Memory" was selected to present a poster at one of the Work-in-Progress (WIP) sessions at the 60th Design Automation Conference (DAC), July 9-13 in San Francisco, CA.
  • Manuscript titled "CoSeP: Compression and Content-based Selection Procedure to improve lifetime of encrypted Non-Volatile Main Memories" was selected to present a poster at one of the Work-in-Progress (WIP) sessions at the 59th Design Automation Conference (DAC), July 10-14 in San Francisco, CA.
  • Finalist of the Intel India Ph.D. fellowship, 2022.
  • Finalist of the Qualcomm Innovation Fellowship for Ph.D, 2021.
  • Presented poster titled "Reuse Distance based Victim Cache for effective Utilization of Hybrid Main Memory Systems" at ARCS 21, (ACM India Annual Event).
  • Qualified AIEEE 2009 and GATE 2014.
  • Rank Holder at 10th board (19th rank in the state) examination conducted by SEBA.



Publication